基于NIOS II的扩展FPGA培训

Expanded FPGA Training with NIOS II

216 次查看
科罗拉多大学波德分校
Coursera
  • 完成时间大约为 16 个小时
  • 中级
  • 英语
注:本课程由Coursera和Linkshare共同提供,因开课平台的各种因素变化,以上开课日期仅供参考

你将学到什么

Apply FPGA design and implementation to engineering problems/challenges.

Understand the components of a soft core processor system inside an FPGA and apply this understanding to a project.

Categorize the types of external memory interfaces supported by FPGA devices.

Employ computer aided design tools to design, verify, and implement embedded systems.

课程概况

The complexity of digital logic designs requires understanding of large scale devices such as Field Programmable Gate Arrays (FPGAs) to realize solutions. Implementation in discrete components is nearly impossible to realize and debug due to the growing complexity of solutions. Integration of processor capability into one platform enables reduction in size and conservation of power with improved microelectronic hardware. The focus of this specialization is the practical use of Soft Processors with emphasis on testing and debugging in applications of video.

Hands on bring up of DE10-Lite board with expansion into the use of the VGA output interface is provided. Focus on the use of the NIOS II processor to control Video IP for generation of test pattern output after reviewing the sample test pattern demonstration in Verilog. Review of the manual for the implementation of Video IP for display of signals using the Avalon-ST streaming protocol is covered. Tools for the design of systems are provided which include the System Console and TCL scripts for evaluation of board and processor interfaces with custom project, and an embedded Logic Analyzer for probing of signal values to characterize performance and state transition. A traffic light controller and thunderbird tail lights are used to provide hands-on examples.

课程大纲

Hardware setup and verification for DE10-Lite with VGA monitor output

Focus on the use of hardware platform with detailed support for key steps necessary to launch solutions from demonstration folders provided by manufacturer of FPGA systems. Examples provided with an emphasis on video. Additional resources are pointed out for access. Peer review assignment evaluates understanding of key concepts in FPGA design software and interaction with TPG and CVO Video IP blocks.

Methods and approaches for testing FPGA designs

Overview of tools for design verification for functionality and performance. Discussion of system console capabilities using TCL scripts with emphasis on board bring up and processor evaluation. Description of embedded logic analyzer capabilities with triggering for state transition verification and logic operation along with capabilities to store results for data analysis. Brief introduction to external memory evaluation capabilities to be discussed in future modules.

NIOS II IP for Video and Performance Monitoring

This module covers the use of additional Video IP suite modules with emphasis on the bus interfaces used for streaming along with more test modules that are available in System Console for verification. Introduction to custom IP blocks is provided using TCL and the Custom IP capabilities in the Soft Processor environment of Qsys provided by the Intel development tools for FPGA design.

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